Extensive use is currently made of nonvolatile digital data memory devices. Various consumer products, such as personal data assistants (PDAs), cellular telephones, and electronic notebooks require nonvolatile memory devices for storing information in a compact support of large capacity.
A shortcoming of nonvolatile memory devices is a high rate of power consumption associated with their operation. The rate of power consumption is obviously of major consequence to portable products such as those listed above since such devices are typically battery powered.
Most of the power expended to operate such memories goes to charge pump circuits, which are arranged to raise the voltage value above the supply level (usually the battery voltage level) for further supplying a part of the circuitry integrated in the memory device. This power expenditure is a result of high voltages needed to perform such basic operations as program and erase operations in nonvolatile memory devices. Where low voltage supply circuits are utilized, read operations as well as program and erase voltages are higher than the supply voltage.
Thus, providing charge pump circuits that utilize as small of a drain as possible on the power supply for their operation is of significant importance, and the present trend toward ever lower supply voltages for integrated circuits can only increases this importance.
With reference to FIG. 1, a circuit diagram of a typical four-stage Dickson charge pump device includes diodes D1-D5 connected in series, with coupling capacitors C1-C4 each being connected to a node between the diodes D1-D5. The Dickson charge pump circuit also includes an output capacitor CL. The output capacitor CL is connected in parallel with an external load 103. Input clock pulses CLKA and CLKB are of opposite phase with respect to each other. The clock pulses CLKA and CLKB are input to a clock driver 101. The clock driver 101 is provided with a power supply voltage VDD (not shown). An output phase of the clock pulses CLKA and CLKB is represented as φ1 and φ2 respectively. The clock pulse phase φ1 is fed to the capacitors C1 and C3, while the clock pulse phase φ2 is fed to the capacitors C2 and C4.
In a stable state, in which a constant current Iout flows out through the external load 103, an input current to the charge pump device is a sum of a current from an input voltage VDD and a current provided from the clock driver. These currents are as described below, disregarding charging or discharging currents to or from any stray circuit capacitance. During a clock period where φ1 is “high” (i.e., logic “1”) and φ2 is “low” (i.e., logic “0”), an average current of 2·(Iout) flows through each of a plurality of paths in directions depicted in the figure as solid line arrows.
During a subsequent clock period where φ1 is “low” and φ2 is “high,” an average current of 2·(Iout) flows through each of the plurality of paths in directions depicted in the figure as dashed line arrows. An average current of each of these aforementioned currents over a complete clock cycle is Iout. An increased voltage from the charge pump device in the stable state is expressed by equation (1),Vout=Vin−Vd+n(Vφ′−V1−Vd)  (1)where Vφ′ refers to an amplitude of a voltage at each of the connecting nodes induced through the coupling capacitor by a change in the clock pulse; V1 denotes a voltage drop due to the output current Iout; Vin denotes the input voltage, which is usually set at VDD in positive voltage boosting and at 0 volts in negative voltage boosting; Vd refers to a forward bias diode voltage; and n denotes a number of stages of pumping.
Further, V1 and Vφ′ are expressed by the following equations
                              V          1                =                                            I              out                                      f              ⁡                              (                                                      C                    i                                    +                                      C                    s                                                  )                                              ≡                                    T              ·                              I                out                                                                    C                i                            +                              C                s                                                                        (        2        )                                          V                      ϕ            ′                          =                                            V              ϕ                        ·            C                                              C              i                        +                          C              s                                                          (        3        )            where Ci represents a clock coupling capacitance of one of the capacitors C1-C4; Cs is a stray capacitance at each of the connecting nodes; Vφ is an amplitude of the clock pulses; f is a frequency of the clock pulses; and T is a clock period of the clock pulses. Power efficiency, η, of the charge pump device is calculated, disregarding charging/discharging currents from/to the clock driver to/from the stray capacitors and assuming Vin=VDD, by
                    η        =                                                            V                out                            ·                              I                out                                                                    (                                  n                  +                  1                                )                            ⁢                                                V                  DD                                ·                                  I                  out                                                              ≡                                    V              out                                                      (                                  n                  +                  1                                )                            ⁢                              V                DD                                                                        (        4        )            
Consequently, the charge pump device boosts the voltage by successively transferring electric charge to a next stage using a diode as a charge transfer device. However, an MOS transistor is easier than a PN junction diode to implement in a semiconductor integrated circuit due to fabrication compatibility within the manufacturing process.
Thus, MOS transistors, as indicated in FIG. 1B, are used as the charge transfer devices in place of the diodes D1-D5 of FIG. 1A. Using MOS transistors, Vd in equation (1) is replaced with Vth, where Vth represents a threshold voltage of the MOS transistor.
FIG. 2 shows a simple ring oscillator that can be used to drive either of the Dickson charge pump circuits shown in FIGS. 1A and 1B. The ring oscillator is composed of a number of inverter elements 2031, 2032, . . . , 2035 connected in series. An input NAND gate 201 provides a means for disabling the oscillator when a low voltage signal is presented at a first input of the NAND gate 201, labeled “clk_en.” Each oscillator output produces signals, clk and clk, which are stable (i.e., φ1=1, φ2=0) when a signal at clk_en is low. When enabled, the input NAND gate 201 inverts the signal from a second input of the NAND gate 201. The signal is then propagated through the inverter elements 2031, 2032, . . . , 2035 back to the second input of the NAND gate 201. This process continues until the enable signal at clk_en goes back to low. The amount of time taken to propagate the signal back to the second input is determined by a delay of each of the inverter elements 2031, 2032, . . . , 2035. This inverter delay is dependent on the supply voltage VDD; the supply voltage VDD determines a maximum gate-source voltage that can be applied to transistors within each of the inverter elements 2031, 2032, . . . , 2035. The gate-source voltage determines a current drive for each of the inverter elements 2031, 2032, . . . , 2035, thus determining the propagation delay. A signal that is present at f1 is provided to a first clock driver portion 204, which is comprised of a NAND gate 205, a first inverter 2071 and a second inverter 2072, all connected in serial manner with each other. The first clock driver portion 204 produces an output “clk.” A signal at f0 is provided to a second clock drive portion 208, which is comprised of a NAND gate 209, a first inverter 2111 and a second inverter 2112, all connected in serial manner with each other. The second clock driver portion 208 produces an output “ clk.” The output signals clk and clk are 180° out of phase with respect to each other.